1. Field of the Invention
The present invention relates to a method of fabricating a silicon island in semiconductor substrate. More particularly, the invention provides a method of fabricating a silicon island of mono-crystalline silicon for making electronic devices.
2. Description of the Related Art
Since Silicon-On-Insulator (SOI) devices are fabricated on a thin silicon film on a insulator, the parasitic capacitance of the source/drain of MOSFET to the substrate below is greatly reduced and the operation speed is substantially improved compared to conventional microelectronic circuit fabrication on bulk silicon substrate (Bulk Devices). Thus SOI have tremendous advantage for very large scale integration (VLSI) of electronic devices over conventional Bulk Devices. In SOI fabrication, the channel length of the source/drain is reduced thereby decreasing the area and effectively increasing the integration of a semiconductor device. Additionally, device isolation of the SOI devices can be easily achieved with shallow trench isolation (STI) techniques by simply etching off unnecessary parts of silicon film surrounding areas to be used for SOI devices.
However, SOI devices are difficult to fabricate and expensive. Additionally, SOI devices have inherent drawbacks due to build-up of hot carrier generated during the operation. During SOI operation, from time to time, a high electric field concentrates around the drain region. Electric charges flowing in the channel are accelerated by the strong electric field around the drain and generates the opposite electric carriers by impact ionization which then flows back to the body of the device. Since SOI is completely isolated electrically from the substrate below, the created carriers cannot be drained into the substrate and thus builds up in the body of the SOI, this causes floating body effect, i.e. a shift of electrical potential in the body of SOI device with carrier build up. This floating body effects then induces undesirable transition in device performance such as change of threshold voltage with time.
Therefore, holes are confined inside the SOI device body. When a forward voltage is applied between the source and the body, holes in the body start to flow out of the source forming parasitic bipolar action path. With this new electron path formed away from gate electrode besides proper channel current path at the interface between silicon and gate oxide, the SOI device shows unexpected irregular operation so called kink effect.
Further, formation of electrical pathways through the insulating material requires process steps to open a small hole through the insulating region whose dimensions become less than 0.25 mm in the deep sub-micron device era (if the hole is larger compared with the insulating region, the device loses advantages of SOI device). Formation of such small holes precisely aligned within the insulating region whose dimensions are less than 0.25 mm is extremely difficult and almost impractical as a ULSI manufacturing method. Furthermore, the method requires a crystallization step even for constructing a single level planar circuit, which is inefficient, when a single crystal level is already available on the original substrate surface.
Therefore, improved devices structure and a simple fabrication which realize high speed operation as with conventional SOI devices but without any adverse effects related to the charge build-up is highly desired. In order to overcome the above defects a thin-foot charge drain beneath the conventional SOI structure to sweep out undesirable charge build-up generated by hot carrier effects during device operation desirable.
Referring to FIG. 1A, is a schematic diagram illustrating a conventional SOI, a silicon nitride film 102 about 2000 A thick is formed on a silicon substrate 100 using a CVD technique, a photoresist mask 104 is formed.
Next, referring to FIG. 1B, a reactive ion etching (RIE) is performed to penetrate etching through silicon nitride layer 102 and the underlying silicon substrate 100, forming a trench 105 forming a silicon island structure 112. During the etching process, a thin passivation layers 106 are formed on the sidewall.
Next, referring to FIG. 1C, an anisotropic (chemical) dry etching using CF4/O2 plasma is performed. The passivation layers 106 forms a protective layer on the sidewalls and is unaffected by etching. While the horizontal bottom surface has no passivation layers are etched eroding the bottom surface and forming a foot of a silicon island 210 as shown.
However, there is a problem in fabricating a silicon island with a thin foot region under the island using the method as described above. It is very difficult to control the etching process for obtaining a desired foot thickness in a deep submicron device, often over-etching and breaking off of the structure 112 occurs.
Therefore, in consideration of the above problems, the present invention provides a improved device structure and more particularly providing an improved fabrication method for forming a silicon island having a thin foot region under the silicon island.
The invention provides a fabrication method for forming a silicon island. A first diffusion-barrier layer including silicon oxide is formed on a semiconductor substrate. The first diffusion-barrier layer and the silicon substrate are patterned to a depth to form a trench. A second diffusion-barrier layer including silicon oxide or BPSG is formed and patterned to form a first spacer on the sidewall of the trench. An anisotropic etching is performed to expose a portion of the sidewall of the trench. A dielectric layer is formed over the substrate, dopants are introduced into the dielectric layer. The doped dielectric layer is patterned to form a second spacer. Some dopants from the doped dielectric layer diffuse into the substrate to form doped regions. An isotropic etching is performed. Since the etch-rate of the doped silicon oxide is higher than the undoped silicon oxide, the doped silicon oxide is easily and rapidly etched first. As the undoped silicon portion of the silicon substrate is exposed, the etching rate is substantially decreased or stopped forming a thin foot underneath the silicon island. Thus the isotropic etching can be easily controlled.
The invention provides a fabrication method for forming a silicon island. A silicon substrate is provided. A first diffusion-barrier layer is formed on the silicon substrate. The first diffusion-barrier and the silicon substrate is patterned to form a trench, wherein a silicon island structure is formed. A conformal second diffusion-barrier layer is formed on the first diffusion-barrier layer and inside the trench. The second diffusion-barrier layer is patterned to form a first spacer. A directional etching is performed to expose a portion of sidewall inside the trench. A step of blanket doping is performed on the silicon substrate. An etching step is performed on the substrate to form a thin foot region underneath the silicon island structure.
It is to be understood that both the foregoing general description and the following detailed are exemplary and are intended to provide further explanation of the invention as claimed.